Conventional integrated memory circuits, such as random access memories (RAMs), both of the static type (sRAMs) and dynamic type (dRAMs), read-only memories (ROMs), both of the mask-programmed type and of the electrically programmable type (including PROMs, EPROMs, EEPROMs and EAROMs), and other memories such as dual-port RAMs and FIFOs, are generally organized into rows and columns. This row-by-column organization applies both to the physical arrangement of the memory cells in an array, and also to the electrical operation of the memory itself. Certain ones of the address terminals are used in selection of a row of memory cells in the array, and certain others are used in the selection of a column, providing access to one or more memory cells in the selected row. It should be noted that in dRAMs, the row and column addresses are generally time-multiplexed at the device address terminals.
Where the number of memory cells is quite large, such as on the order of 2.sup.20 storage locations (i.e., 1 Mbits), the physical size of the memory array accordingly becomes quite large, even when fabricated with state-of-the-art technology which allows feature sizes of less than one micron. Besides the larger physical memory size necessary for such memories, the selection of a row, of the memory array results in the activation of a larger number of memory cells. Such activation is generally performed by a row decoder presenting an active logic level on a long conductor commonly referred to as a row line, or word line. The active level on this conductor connects the memory cells in its associated row to their respective bit lines, in effect placing the storage cells in communication with sense amplifiers.
The number of memory cells activated for each row, of course, depends upon the storage capacity of the memory and the organization of the memory array. For example, in a "square" 1 Mbit memory array having 1024 columns by 1024 rows, the selection of an entire row activates 1024 memory cells, and connects this number of memory cells to bit lines for the communication of their stored data to a sense amplifier. Accordingly, the power consumption required for the selection and energizing of an entire row of memory cells becomes larger with such higher density memories. In sRAM devices where a single row address may be presented for a relatively long period of time (e.g., for sequential operations to multiple numbers of memory cells in the same row), the active power consumed by the device is quite high. It is therefore desirable to limit the duration for which an entire row is activated.
The problem of high active power dissipation is especially acute in memories such as dual-port RAMs and FIFOs. In each of these memory types, selection and simultaneous enabling of two rows of memory cells is often performed in accomplishing simultaneous read and write operations. Accordingly, the active power for such memories, for such simultaneous operations, is double that of a similarly-sized single port RAM.
One prior technique for limiting the duration of row line selection is to "time-out" the energizing of the row line, so that after a row is initially accessed, the row line signal is returned to an inactive logic level. Storage of the contents of the memory cells in the row is provided by sense amplifiers in such an arrangement, so that repeated read operations may be performed without requiring that the row line be energized. This technique monitors transitions at the data input terminals, indicative of a write operation, in which case the row line signal is again energized to allow for the writing of data into the memory cells of the selected row. It has been observed that this technique is subject to error in the case where transitions at the data inputs are relatively slow, as such slow transitions may possibly be undetected by the transition detection circuit. In addition, the presence of tri-state conditions on the data bus to which the input terminals are connected may present an erroneous transition to the detection circuit.
Another prior technique for limiting power dissipation is the reduction of the active bit line loads served by a particular row line. For example, multiple row decoders may be provided for each "row", so that a combination of the row address and the most significant column address bits selects a row decoder, with the number of memory cells in each selected row reduced. While such a technique reduces the active power, the size of the integrated circuit chip must increase in order to implement additional row decoders. This not only increases the cost of manufacture of the circuit, but also may present problems in fitting the circuit into the desired package size.
Another prior technique for selecting a portion of a row line is described in Sakurai, et al., "A Low Power 46 ns 256 kbit CMOS Static RAM with Dynamic Double Word Line", IEEE J. Solid State Circuits. Vol. SC-19, No. 5 (IEEE, Oct. 1984), pp. 578-585. The technique described in this article uses two word lines in accessing each bit, one being a main word line MWL and the other being smaller section word lines SWLs. As shown in FIG. 2 of the Sakurai et al. article, the main word line is presented by the row decoder, with NOR gates controlled by the column decoder for driving the section word lines; the NOR gates for each section are connected in parallel relative to each other, all off of the main word line. In this way, only the portion of the row in the selected section is accessed. However, this scheme requires an additional level of conductor, namely a second aluminum layer (see page 579, right hand column, and Table II). Such additional process complexity is, of course, quite costly. In addition, the main word line from the row decoder must remain energized for the full duration of the time that the selected section word line is to remain active.
It is therefore an object of this invention to provide a memory architecture which provides for reduced power dissipation by limiting the number of memory cells selected after a row line has been energized.
It is a further object of this invention to provide such an architecture which does not require additional row decode circuitry.
It is a further object of this invention to provide such an architecture which can be implemented without the addition of another metal, or other conductor, layer.
It is a further object of this invention to provide such an architecture which includes latched repeaters which require reduced layout area.
It is a further object of this invention to provide such an architecture which includes latched repeaters which have simpler and more stable operation.
Other objects and advantages of the invention will be apparent to those of ordinary skill in the art having reference to the following specification together with the drawings.